Supermicro P4SGA+ User Manual download pdf (Page 64)

SUPER P4SGA/P4SGL/P4SGR/P4SGE User's Manual

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Active to Precharge Delay

This item regulates the number of memory clock cycles allowed for memory

refresh charging. The options are "7", "6" and "5". Shorter timings increase

system memory throughput at the risk of lacking sufficient refresh charge.

DRAM RAS# to CAS# Delay

This item regulates the number of memory closk cycles between strobing a

row address (RAS) and a column address (CAS). Shorter numbers of clock

cycles improve system memory performance at the risk of missing data.

The options are "3" and "2".

DRAM RAS# Precharge

This item regulates the number of system memory clock cycles for RAS

precharging. The options are "3" and "2".

Memory Frequency For

This item regulates system memory frequency. The options are "PC100",

"PC133" and "Auto".

Buffer Strength Control

Highlighting this item and pressing <Enter> will display a sub menu that

allows you to control various buffer strengths.

System BIOS Cacheable

If enabled, the system BIOS information stored in the BIOS ROM (Read Only

Memory) chip will be written and temporarily stored in the "cacheable"

memory section of the CPU, giving the CPU faster access to the information.

The options are "Disabled" and "Enabled".

CAS Latency TIme

This item regulates memory column address strobe (CAS) timing. The

settings are "1.5", "2", "2.5" and "3".

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Supermicro P4SGA+ User Manual Page 64