Supermicro HMT325R7BFR8C-H9 Specifications download pdf (Page 8)

Rev. 1.6 / Dec. 2010 8

RESET

Input

Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when

RESET

is HIGH. RESET must be HIGH during normal operation.

RESET

is a CMOS rail-to-rail signal with DC high and low at 80% and 20% of V

, i.e.

1.20V for DC high and 0.30V for DC low.

Input /

Output

Data Input/ Output: Bi-directional data bus.

DQU, DQL,

DQS, DQS

DQSU, DQSU

DQSL, DQSL

Input /

Output

Data Strobe: output with read data, input with write data. Edge-aligned with read data,

centered in write data. The data strobe DQS, DQSL, and DQSU are paired with differential

signals DQS

, DQSL, and DQSU, respectively, to provide differential pair signaling to the

system during reads and writes. DDR3 SDRAM supports differential data strobe only and

does not support single-ended.

TDQS, TDQS

Output

Termination Data Strobe: TDQS/TDQS

is applicable for x8 DRAMs only. When enabled via

Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance

function on TDQS/TDQS

that is applied to DQS/DQS. When disabled via mode register A11

= 0 in MR1, DM/TDQS will provide the data mask function and TDQS

is not used. x16

DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.

No Connect: No internal electrical connection is present.

No Function

DDQ

Supply DQ Power Supply: 1.5 V +/- 0.075 V

SSQ

Supply

DQ Ground

Supply

Power Supply: 1.5 V +/- 0.075 V

Supply

Ground

REFDQ

Supply

Reference voltage for DQ

REFCA

Supply

Reference voltage for CA

Supply

Reference Pin for ZQ calibration

Note:

Input only pins (BA0-BA2, A0-A15, RAS

, CAS, WE, CS, CKE, ODT, DM, and RESET) do not supply termination.

Symbol Type Function

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 33 34

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Supermicro HMT325R7BFR8C-H9 Specifications Page 8

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